1. Field of the Invention
The present invention relates to a sense amplifier in use with a semiconductor memory device, such as a read only memory (ROM) and a random access memory (RAM).
2. Description of the Related Art
In a semiconductor memory device, such as a read only memory (ROM) or a random access memory (RAM), the potential in a bit line is varied by data read out of a memory cell. The variation of this bit line potential is very slow and difficult to detect. To cope with this, a sense amplifier is coupled with a bit line, and senses and amplifies variations in that bit line. The output signal of the sense amplifier is outputted as read out data.
A typical arrangement of the sense amplifier is shown in FIG. 1. In this figure, N channel MOS transistors N1 to N6 serve as memory cells, and their gates are respectively connected to word lines WL1 to WL6. Drive signals IN1 to IN6 are externally applied to the word lines WL1 to WL6. A sense amplifier SA is connected to a bit line BL, and is made up of P channel MOS transistors TP1 and TP2, and CMOS inverters IV1 and IV2.
An operation of the sense amplifier SA will be described with reference to FIGS. 2 and 3.
FIG. 2 shows a timing chart describing a transient state of the arrangement of FIG. 1 in which the potential in the bit line BL drops, viz., an output signal OUT changes its level from a high (H) level to a low (L) level. As shown in FIG. 2, in an initial state of a period A, all of the drive signals IN1 to IN6 are in an L level state. All of the transistors N1 to N6 are in an off state. A precharge signal PR is H level. Under this condition, the transistor TP1 is in an off state. The transistor TP2 is in an on state due to the L level output signal of the CMOS inverter IV1. By means of this transistor TP2, the potential in the bit line BL is maintained at an H level.
During a period B, the precharge signal PR first goes low (L), and one of the word line drive signals IN1 to IN6, for example the signal IN1, is pulsed from a low level to a high level. Consequently, the transistor TP1 is turned on, and the cell transistor N1 is turned on. The potential of the bit line BL gradually drops through the turned on transistor N1. When the potential of the bit line BL falls below the threshold voltage VTH1 of the inverter IV1, the output signal of the inverter IV1 starts to change its level from the L level to the H level. When the output signal of the inverter IV1 rises and exceeds the threshold voltage VTH2 of the inverter IV2, the output signal OUT of the inverter IV2 starts to change its level from the H level to the L level. The transistor TP2 is turned off by the H level output signal of the inverter IV1.
As can be seen, when the output signal OUT changes its potential level from the H level to the L level, the operating speed of the sense amplifier SA is determined by the propagation delay time TpHL from the instant that the drive signal IN1 has gone high, till the output signal OUT has gone low.
FIG. 3 shows a timing chart describing a transient state of the arrangement of FIG. 1 in which the potential in the bit line BL rises, viz. the output signal OUT changes its level from the low level to the high level. In an initial state of period A, one of the drive signals IN1 to IN6, for example the signal IN1, is in the H level. Accordingly, of the transistors N1 to N6, the transistor N1 alone is in an on state. The precharge signal PR is also in the H level. The transistor TP2 is placed in an off state by the H level output signal of the CMOS inverter IV1.
Subsequently, during period B, the precharge signal PR first goes low (L), and the word line drive signal IN1 goes low. Accordingly, the transistor TP1 is turned on, and the cell transistor N1 is turned off. In turn, the potential of the bit line BL starts to rise until it exceeds the threshold voltage VTH1 of the first inverter IV1. At this time, the output potential of the first inverter IV1 starts to change its potential level from a high level to a low level. When the output potential of the first inverter IV1 falls below the threshold voltage VTH2 of the second inverter IV2, the output signal of the second inverter IV2, viz. the output signal OUT, goes high. The low output signal of the inverter IV1 causes the transistor TP2 to be turned on, as a result of which, the potential of the bit line BL is kept high.
As can be seen, when the output signal OUT changes its potential level from low to high, the operating speed of the sense amplifier SA is determined by a propagation delay time TpLH from the instant that the precharge signal PR has gone low, till the output signal OUT has gone high.
In the sense amplifier SA, the propagation delay times TpLH and TpHL are both large, and hence the operating speed is low.
This problem will be discussed in more detail. It is assumed now that the on-resistance of the transistor TP1 (the resistance between the source and drain of the transistor TP1 when TP1 is in a conductive state) is RP1, the on-resistance of the transistor TP2 is RP2, the on-resistance of each of the cell transistors N1 to N6 is RN, the high level potential is VCC, the low level potential is 0 V, and the threshold voltage VTH1 of the first CMOS inverter IV1 is 2.5 V. In order that during the period B in FIG. 2, the potential VBL of the bit line BL is below the threshold voltage VTH1 of the first inverter IV1, the following relation must hold ##EQU1## To solve the above relation, we have The inequality (1) teaches that in order that the bit line potential VBL is lower than the threshold voltage VTH1, the parallel resistance ##EQU2## of the transistors TP1 and TP2 must be larger than the on-resistance RN of the cell transistor N1.
Generally, in semiconductor memory devices, the geometrics of the cell transistors, which are formed on the chip, are the smallest allowable within the design rules. Therefore, the on-resistance RN is relatively large. Therefore, to set the parallel resistance of the transistors TP1 and TP2 to be larger than the on-resistance RN of the cell transistor, it is necessary to set the on-resistances RP1 and RP2 of the transistors TP1 and TP2 so as to be relatively large.
In the case of the sense amplifier SA of FIG. 1, the on-resistance of each of the cell transistors N1 to N6 to lower the potential of the bit line BL, and the on-resistance of each of the transistors TP1 and TP2 to raise the bit line potential are both relatively large. It is for this reason that much time is required for charging and discharging the bit line BL, the propogation delay times TpLH and TpHL are long, and consequently the operation of the sense amplifier SA is slow.